| 摘要 |
A multiplier circuit having a rounding-off function. A multiplier circuit has a smaller circuit size and operates at a higher speed by using a rounding half adder. An addition processing part which receives partial products from a partial product generating part, includes in its first stage two half adders and a rounding half adder. Its second stage includes three full adders, as does its third stage. Its fourth stage includes a three-bit carry look ahead adder. The output of the rounding half adder is the sum of the two inputs and an auxiliary value, such as 1. By utilizing the rounding half adder, a separate rounding circuit is unnecessary.
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