发明名称 |
Logic gate size optimization process for an integrated circuit whereby circuit speed is improved while circuit area is optimized |
摘要 |
An integrated circuit, when designed, must adhere to timing constraints while attempting to minimize circuit area. In order to adhere to timing specifications while arriving at a near-optimal circuit surface area, an iterative process is used which selectively increases logic gates sizes by accessing logic gates from a memory stored logic gate library. A circuit representation is read along with timing constraints for circuit paths. Each circuit path in the circuit is processed to find it's actual circuit path delay. A most out-of-specification circuit path (in terms of speed) is chosen in the circuit and a sensitivity calculation is performed for each logic gate in the most out-of-specification circuit path. The logic gate in the circuit path with the maximized sensitivity (sensitivity= DELTA speed/ DELTA area) is increased in size by accessing a larger gate in the library in order to improve speed at the expense of area. The above process continues iteratively until no out-of-specification circuit paths are found.
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申请公布号 |
US5619418(A) |
申请公布日期 |
1997.04.08 |
申请号 |
US19950390210 |
申请日期 |
1995.02.16 |
申请人 |
MOTOROLA, INC. |
发明人 |
BLAAUW, DAVID T.;NORTON, JOSEPH W.;JONES, LARRY G.;MISRA, SUSANTA;BAHAR, R. IRIS |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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