| 摘要 |
A read circuit for a memory cell includes a sense amplifier and an equilibrate circuit. The sense amplifier is coupled to the memory cell via a pair of data lines, and amplifies the data signals that the memory cell provides. The equilibrate circuit is coupled to the sense amplifier, receives an equilibrate signal, and, when the equilibrate signal has an active level, equilibrates the sense amplifier. When the equilibrate signal has an inactive level, the equilibrate circuit causes the sense amplifier to draw substantially zero supply current, regardless of the levels of any signals on the data lines. The read circuit may also include an enable circuit that receives an enable signal and is coupled to the sense amplifier. When the enable signal has an active level, the enable circuit allows the sense amplifier to amplify the data signals on the data lines. When the enable signal has an inactive level, the enable circuit prohibits the sense amplifier from amplifying the data signals on the data lines.
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