| 摘要 |
PROBLEM TO BE SOLVED: To reduce jitters in a synchronized clock concerning a clock extracting circuit to be used for a device for demodulating a multi-phase modulated signal or an orthogonal amplitude modulated signal. SOLUTION: A clock frequency component is extracted from an input signal 1 by a digital filter 2, phase difference between that output signal and a clock 7 is detected by a phase comparator 3, an oscillator 6 is controlled by a loop filter 5 so that the phase difference can be '0', and the clock 7 synchronized with the clock frequency component contained in the input signal 1 is outputted. In this case, a selection circuit 9 switches the coefficient train of the digital filter before and after the synchronization of the clock corresponding to a signal from a synchronism decision circuit 8. Before the synchronization, the pull-in range of frequency is widened by widening the passing band of digital filter but after the synchronization, jitter in the clock is suppressed low by narrowing the passing band. |
