发明名称 |
DIGITAL CIRCUIT WITH GEOMETRICAL ARRANGEMENT AND CHANNEL STOP OF TRANSISTOR WHICH IS CAMOUFLAGED FOR REVERSE ENGINEERING |
摘要 |
<p>PROBLEM TO BE SOLVED: To inhibit reverse engineering of an integrated circuit by arranging different logic cells in substantially the same spatial patterns and making the logical functions of the cells not distinguishable from a transistor pattern, and then, deciding the logical function of the cells by the pattern of conductive ion implantation interconnections. SOLUTION: All p-channel transistors 2-6 and n-channel transistors 12-16 in an array have substantially the same sizes and geometric structures. Interconnections are performed through the injection of a doping impurity into the substrate between desired source and drain. In other words, the implanting sections of the source and drain are expanded on either one side section of a transistor provided with a tap including a source tap ST and a drain tap DT and the interconnection is executed by using the tap and its adjacent connector C. Therefore, the reverse engineering of an integrated circuit can be prevented.</p> |
申请公布号 |
JPH0992727(A) |
申请公布日期 |
1997.04.04 |
申请号 |
JP19960098836 |
申请日期 |
1996.04.19 |
申请人 |
H II HOLDINGS INC D B EE FUSE ELECTRON |
发明人 |
JIEIMUSU PII BAUKUSU;RATSUPU WAI CHIYOU;UIRIAMU EMU KURAAKU JIYUNIA |
分类号 |
H01L21/3205;G06F21/06;G11C7/24;H01L21/82;H01L21/822;H01L23/52;H01L27/02;H01L27/04;(IPC1-7):H01L21/82;H01L21/320 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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