发明名称 OUTPUT CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce ringing and to attain high speed operation by properly controlling the delay of a switching time of an output NPN bipolar transistor(TR). SOLUTION: Plural stages of delay circuits 9 are connected and the same number of output impedance control circuits 50 as those of the delay circuits 9 are provided, and 1st, 2nd and 4th input terminals and output terminals of each output impedance control circuit 50 are connected together and the 3rd input terminal connects to an output of a corresponding delay circuit 9 among the plural stages of the delay circuits 9. Ringing is suppressed by properly selecting a ratio of the gate width of TRs 1, 3, an emitter area ratio of TRs 6, 7 to be nearly 1: 1 to 0.5 and selecting the delay time of each delay circuit 9 to be 1×10<-9> to 4×10<-9> second. Since not only one output impedance control circuit 5 is in use but also some of the control circuits 5 may be added as required, the effect of suppressing ringing is improved.
申请公布号 JPH0993112(A) 申请公布日期 1997.04.04
申请号 JP19950251537 申请日期 1995.09.28
申请人 NEC CORP 发明人 WATARAI SEIICHI
分类号 G06F13/38;H03K19/0175;H03K19/08;(IPC1-7):H03K19/017 主分类号 G06F13/38
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