| 摘要 |
<p>PROBLEM TO BE SOLVED: To prevent malfunction of a data valid period generating circuit by synthesizing a frame top signal, a data valid period end pulse and an output of a DFF at a gate circuit and giving the output of the gate circuit to a data input terminal of the DFF. SOLUTION: A valid period end pulse generating circuit 32 decodes the output of counters 24-26 to generate a pulse representing only one period of a final clock signal of a valid period signal. Furthermore, each of frame top signal detection circuits 21-23 have a data input terminal 0 and a clock input signal terminal receiving a clock signal. A D flip-flop 23 provides the output of data corresponding to data received at a terminal D when the clock signal is received. Gate circuits 21, 22 synthesize the frame top signal and the output of the D flip-flop, outputs of the circuits 21, 22 are given to the terminal D of the D flip-flop to simplify the configuration.</p> |
