发明名称 CELL LAY-OUT METHOD
摘要 PROBLEM TO BE SOLVED: To lay out memory cells as small as possible. SOLUTION: The size of a power supply block 42 is so decided that the value obtained by adding the width (3) of the block 42 and the width (2) of a memory block 41 becomes the magnification of natural number of a lattice interval in automatic layout and wiring. Even if the memory cell 410 is laid out without being conscious with the interval of the aligning interconnection, the terminal position of the memory can be aligned to the lattice by the dimensional regulation of the block 42. Thus, the limit by the interval is excluded to make it possible to perform the minimum lay-out of the cell 410.
申请公布号 JPH0992797(A) 申请公布日期 1997.04.04
申请号 JP19950269390 申请日期 1995.09.22
申请人 HITACHI LTD 发明人 KATO KEI
分类号 H01L21/822;H01L21/82;H01L21/8242;H01L27/04;H01L27/108 主分类号 H01L21/822
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