The component includes an n-type semiconductor layer (2) deposited in the main surface of a heavily doped n-type substrate (1). The layer forms a pn-junction with a p-type body section (16), with the body section ending at a side wall (51) of a concave section (50) of the semiconductor layer surface. In the body section is an n-type source region (4) and a channel region (5) on the concave section side wall. The channel region is at least covered by a gate insulating film (8), on which is deposited a gate electrode. The concave section is of a grid depression pattern over the semiconductor layer surface.
