PLANAR ELECTRONIC NETWORK

摘要

A planar electronic network of passive electronic components on a chip are formed in a mass-producible method on a rigid substrate in a manner designed to maximize repeatability of the process. The wafer is diced into individual chips. The resulting chip is a network of single or multi-layer inductors along with resistors and capacitors, all of inherently sealed construction. The process utilized is a print-and-repeat style in which conductor paths are formed by successive plating operations to form a continuous circuit path.