发明名称 Verfahren zur Datenerfassung für einen Logikanalysator
摘要 A logic analyzer stores the activity around the last in a series of triggering events while also storing the activity around several other triggering events immediately preceding the last trigger. The acquisition memory is first partitioned into a number, N, of memory sections and the trigger condition of interest is defined. Then repeated acquisitions are performed using this same trigger condition. At first, data from each of these acquisitions is stored in each one of the number of memory sections. When all of the memory sections have been filled once, if the trigger condition is still occurring, the acquisition memories are reused in the same order in which they were originally used as many times as necessary until it is ascertained that the trigger condition is no longer occurring or some external condition has changed, at which time the logic analyzer is stopped. One of the memory sections then contains the data that occurred in the vicinity of the last trigger. Another of the memory sections contains data reflecting the activity that immediately preceded the stopping of the logic analyzer. The remaining N-2 memory sections contain data that occurred in the vicinity of the triggers that immediately preceded the last trigger. Timestamping the acquired data allows the timing relationships involved to be reconstructed.
申请公布号 DE69028265(T2) 申请公布日期 1997.04.03
申请号 DE1990628265T 申请日期 1990.07.24
申请人 TEKTRONIX, INC., BEAVERTON, OREG., US 发明人 JACKSON, RONALD M., PORTLAND, OREGON 97225, US
分类号 G01R13/28;G01R31/3177;G06F11/25;G06F11/34;G06F17/40;(IPC1-7):G06F11/22;G06F11/30 主分类号 G01R13/28
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