Hochgeschwindigkeitstestschaltkreis für eine Halbleiterspeichervorrichtung

摘要

A test circuit for a semiconductor memory device with multiple data lines comprises switch means SW and a comparator COMP. The switch means SW sequentially connects each of a plurality of lines to at least one output sensing amplifier DA whilst the comparator COMP compares the output signals from said amplifier(s) DA. A shift register SR and an internal clock ICLK may be employed in sequentially selecting the data line to be connected to an output sensing amplifier DA via the switch means SW. A predetermine number of data lines may be connected sequentially to respective output sensing amplifiers DA and comparators COMP. The comparators COMP compare the series of inputs from predetermined groups of data lines and identifies whether the device is bad or not.