发明名称 |
Bust mode data transfer in a data processing system |
摘要 |
<p>A data processing system (10) flexibly interfaces with both a variety of memory devices and external peripheral devices. A control register (94) is provided for dynamically controlling a timing relationship for read and write accesses executed by the system. A first set of bits (PA) in the control register provides timing control for an initial amount of time required to read a first data value from an external device. A second set of bits (SA) in the control register provides timing control for each successive amount of time required to read a successive data value from the external device. <IMAGE></p> |
申请公布号 |
EP0766181(A2) |
申请公布日期 |
1997.04.02 |
申请号 |
EP19960115277 |
申请日期 |
1996.09.24 |
申请人 |
MOTOROLA, INC. |
发明人 |
MOYER, WILLIAM C.;KIRTLAND, CHARLES;ARENDS, JOHN H. |
分类号 |
G06F12/00;G06F13/42;G06F15/78;(IPC1-7):G06F13/42 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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