发明名称 Computer system which switches bus protocols and controls the writing of a dirty page bit of an address translation buffer
摘要 An electronic computer which uses different bus protocols to transfer information for processor-to-processor communication and for processor-to-peripheral communication. The electronic computer includes an address buffer translator which translates a virtual address to a physical address and produces a bus protocol specifying signal. A bus interface changes bus protocols in accordance with the bus protocol specifying signal in order to permit a transfer of a physical address and data on the bus. In another embodiment, when the data in a cache memory is changed, a dirty bit for the cache memory is set but a corresponding dirty bit in the address translation buffer is not changed until a copy-back operation from the cache memory to a main memory occurs. The dirty page bit of the address translation buffer is changed utilizing software.
申请公布号 US5617553(A) 申请公布日期 1997.04.01
申请号 US19950429103 申请日期 1995.04.26
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MINAGAWA, KENJI;AIKAWA, TAKESHI;SAITO, MITSUO
分类号 G06F9/38;G06F12/10;(IPC1-7):G06F9/06 主分类号 G06F9/38
代理机构 代理人
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