发明名称 Arbitration circuit capable of changing the priority and arrival time of nonselected requests
摘要 A parallel computer network wherein an arbitration circuit for performing arbitrating operation over a plurality of processing requests at the same time at high speed is provided in a crossbar network control circuit to thereby prevent the processing requests not selected from being kept awaited for a long time. The arbitration circuit includes a priority bit change circuit which has a plurality of adders for adding a preset value to the priority information of the each awaited processing request and also has a plurality of comparators for detecting the requests being awaited.
申请公布号 US5617545(A) 申请公布日期 1997.04.01
申请号 US19930073075 申请日期 1993.06.09
申请人 HITACHI, LTD.;HITACHI VLSI ENGINEERING CORPORATION 发明人 OGATA, YASUHIRO;TAKEUCHI, SHIGEO;TOBA, TATURU;SHUTOH, SHINICHI;HAMANAKA, NAOKI
分类号 G06F9/48;G06F13/18;G06F13/36;G06F15/173;G06F15/80;(IPC1-7):G06F13/18 主分类号 G06F9/48
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