发明名称 MULTIPROCESSOR SYSTEM AND DATA TRANSMISSION APPARATUS THEREOF
摘要 The bandwidth of the data transfer among a main memory and snoopy caches is improved by solving the bus neck in a multiprocessor system using a snoopy cache technique. Shared bus coupling is employed for an address/command bus requiring bus snoop whereas multiple data paths coupled by an interconnection network are used for the data bus not requiring bus snoop. The multiple data paths reflect the order of the snoopy operations on the order of data transfer such as to maintain data consistency among the caches.
申请公布号 CA2062909(C) 申请公布日期 1997.04.01
申请号 CA19922062909 申请日期 1992.03.12
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 MURATA, HIROKI;SHIMIZU, SHIGENORI
分类号 G06F12/08;G06F15/167;(IPC1-7):G06F15/16 主分类号 G06F12/08
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