| 摘要 |
A flash memory system having a reduced tendency to have its erased cells disturbed during read operations. An array of flash memory cells are arranged into a multiplicity of rows and columns, with all of the cells located in one of array rows has a control gate connected to a common word line and with all of the cells in a column has a drain connected to a common bit line. Control circuitry is used for carrying out memory operations, including program circuitry for programming cells of the array based upon a program input address and read circuitry for reading cells of the array based upon a read input address. The read means functions to apply a read voltage to a selected one of the word lines of the array as determined by the read input address. Disturb limit circuitry is used for limiting the time period that the read circuitry applies the read voltage to the selected one of the word lines.
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