| 摘要 |
The scan test circuit disclosed has a first input terminal and a second input terminal for respectively inputting first data of one bit and second data as serial data, a third input terminal for inputting an operation switching signal for determining a scan operation and a normal operation, an input selector for selecting either the first data or the second data in response to the supply of the operation switching signal and outputting the selected data, a register for holding the selected data as hold data, a first output terminal for outputting first output data, and a second output terminal for outputting second output data. The scan test circuit includes a latch circuit which latches a shift mode signal and generates an operation switching latch signal. A selector selectively outputs either an input data or an input data as a selected signal in response to the supply of the signals. Block tests can be executed with an interval corresponding to two clock pulses immediately after the switching of operations from the scan test operation.
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