发明名称 SYNCHRONOUS PROCESSING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To prevent overflow in a buffer memory even if the interruption/ restoration of a reference clock is repeated. SOLUTION: An input interruption detection circuit 17 discriminates the normality of clocks in plural systems, which are extracted by clock extraction circuits 110-113, specifies the clocks in a prescribed priority among the normal clocks and selects them as reference clocks Ckref. A clock generation circuit 15 generates system clocks Cksys from the reference clocks Ckref and sets them to be read clocks for respective buffer memories 121-123. The input cut detection circuit 17 detects that the clock in an interruption state is restored, and sets write address/read address so that data is written and read from a position almost the half of memory capacity into the corresponding buffer memory at the time of detecting restoration.</p>
申请公布号 JPH0983501(A) 申请公布日期 1997.03.28
申请号 JP19950241277 申请日期 1995.09.20
申请人 TOSHIBA CORP 发明人 IDE KAZUHIKO;TAKAMI MASAYUKI
分类号 H04L13/08;H04L7/00;(IPC1-7):H04L7/00 主分类号 H04L13/08
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