发明名称 PLL CIRCUIT AND DIGITAL SIGNAL PRODUCING DEVICE
摘要 PROBLEM TO BE SOLVED: To make a PLL circuit immune to noise and to stabilize characteristics concerning the PLL circuit to be used as a reproducing clock generating circuit for a digital signal reproducing device. SOLUTION: The compared output of a phase comparator 3 is outputted in the form of a balanced (differential) signal and supplied to a loop filter 4, and the output signal of the loop filter 4 is supplied to the control voltage input terminal of a VCO 5 in the form of the balanced signal. The in-phase component of noise contained in a control voltage can be canceled. Besides, the charging and discharging currents of a capacitor at the loop filter flow through the same conductive type of transistor and the characteristics of the PLL circuit can be prevented from being degraded by difference in the characteristics of elements.
申请公布号 JPH0983357(A) 申请公布日期 1997.03.28
申请号 JP19950257122 申请日期 1995.09.08
申请人 SONY CORP 发明人 SEKINE MASATO;KOTANI YASUTAKA;MIYAGI SHIRO
分类号 G11B20/14;H03L7/08;H04L7/033 主分类号 G11B20/14
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