发明名称 MULTIPLE ADDRESS OUTPUT DEVICE FOR ATM SYSTEM
摘要 <p>PROBLEM TO BE SOLVED: To reduce the storage capacity of an address memory in the multiple address output device of an ATM system, which is provided with plural common buffers for an output highway. SOLUTION: When the main signals of the same cells are to be outputted to the plural designated output highways, a specification means 6 previously stores the identification code of the output highway, which is outputted last, in a specified output highway storage means 7 with the address value of a buffer memory 1 where the main signal is stored. Whenever an address value read means 8 and a main signal read means 9 read the main signals from the buffer memory 1 and they are outputted to one of the plural designated output highways, the specified output highway storage means 7 is referred to. When the same output highway is stored, an idle address qualification means 10 judges that the main signals are outputted to all the designated output highways and the storage/holding of the pertinent signal by the buffer memory 1 is terminated.</p>
申请公布号 JPH0983532(A) 申请公布日期 1997.03.28
申请号 JP19950236765 申请日期 1995.09.14
申请人 FUJITSU LTD 发明人 KOYANAGI TOSHINORI;OTA SHINJI;KATO TSUGIO;SAKURAI HIROYA;FUKAMACHI KAZUHIRO;IDE SHOTARO
分类号 H04Q3/00;H04L12/18;H04L12/28;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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