| 摘要 |
PROBLEM TO BE SOLVED: To provide a short pulse elimination circuit simple in configuration and small in the number of elements by controlling the ON/OFF state of an NMOS transistor(TR) by an input signal. SOLUTION: This circuit has a delay means which delays an input signal V1, an inverter gate 31 which is driven by the output of the delay means, an NMOS TR 32 which turns on and off the supply of low potential power to the gate 31, and PMOS TR 33 which turns on and off the supply of high potential power to the gate 31. The ON/OFF states of both TR 32 and 33 are controlled by the signal V1. Then the positive and negative polarity pulses of width Td or less which are mixed into the signal V1 can be e liminated. |
