发明名称 PARALLEL PROCESSING SYSTEM
摘要 PROBLEM TO BE SOLVED: To increase the synchronization processing speed while suppressing the increase in the amount of hardware by using plural signal lines to transmit the contents of a state storage part to individual processors with prescribed phase differences in parallel by a transmission circuit. SOLUTION: A mutual connection device 2 is provided with a state storage part 2A, where state information of each processor 1 is held, and a transmission circuit 2B which transmits held state information of each processor to all processors 1. Each processor 1 performs processing synchronously with operations of other processors 1 based on state information of each processor 1 transmitted from the mutual connection device 1. Plural signal lines 3 to transmit the state information of each processor 1 from the mutual connection device 2 to all processors 1 are interposed between the mutual connection device 2 and each processor 1, and the transmission circuit 2B successively sends contents of the state storage part 2A to signal lines 3 with prescribed phase differences to transmit them to processors 1 in parallel. Thus, the synchronization processing is executed like a pipeline processing.
申请公布号 JPH0981525(A) 申请公布日期 1997.03.28
申请号 JP19950240298 申请日期 1995.09.19
申请人 FUJITSU LTD 发明人 AMADA TADAO;KOBAYAKAWA KAZUE;KOREKATA KENJI
分类号 G06F15/173;G06F9/46;G06F9/52;G06F15/80 主分类号 G06F15/173
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