发明名称 |
FRAME TRANSFER PREFERENTIAL PROCESSOR |
摘要 |
<p>PROBLEM TO BE SOLVED: To shorten delay time between terminals with high efficiency by processing a transferred frame of a logical path prior to that of another logical path when the real delay time of the former transferred frame becomes larger. SOLUTION: A frame transfer preferential processor is applied to the node 2 of a frame relay network where the plural nodes 2 storing plural terminals 1a-1d by a physical line and the frame is transferred through the plural logical paths 3a and 3b which are fixedly set so as to make communication among the terminals. A real delay time measuring means 4 measures real delay time being time which is actually required for the transfer of the frame from the terminals 1a and 1b to the node 2 on the logical paths 3a and 3b. The permission delay time permitted for the transfer of the frame is previously stored in a permission delay time storage means 5 on the logical paths 3a and 3b. A transfer processing means 6 preferentially transfers the frame where real delay time is larger than permitted delay time compared to a frame where real delay time is judged to be smaller than permitted delay time.</p> |
申请公布号 |
JPH0983567(A) |
申请公布日期 |
1997.03.28 |
申请号 |
JP19950230241 |
申请日期 |
1995.09.07 |
申请人 |
FUJITSU LTD |
发明人 |
TANAKA KATSUMI;TERAI NOBORU |
分类号 |
H04L12/911;H04L12/801;H04L12/841;(IPC1-7):H04L12/56 |
主分类号 |
H04L12/911 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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