| 摘要 |
Address transit detecting circuit of static RAM(SRAM) is made up of the NOR gate(5) that receives address and chip-enable signal(CEX), the delay circuit(61) which delays the output of delay circuit and NOR gate, which inverts the output of the XOR gate to operate exclusive-or logic process, the delay controller which is made up of the first and second standard voltage generating circuit(91,92) to supply standard voltage to control delay time by connect to delay circuit, and the first and second switching means(62,63). The output of XOR gate switches the first standard voltage generating circuit, the output of inverter which inverts the output of XOR gate switches the second standard voltage generating circuit.
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