The invention concerns a hardware configuration with processing units (CTR0, CTR1) operated in microsynchronous parallel operation in order to process ATM information, these processing units being connected at the ATM end to a switching matrix (SN0, SN1) and via a bus interface (B-I) to a central processor. The central processor is used for evaluating error statistics occurring in the processing units and for monitoring the synchronous operation by comparing the processing results. The error statistics data are packed in ATM transmission cells and looped back via the switching matrix to each of the processing units and then fed to the control processor via the bus interface. This system prevents the erroneous display of the loss of microsynchronization when error statistics for the two processing units differ.
