发明名称 INTERCONNECT SCHEME FOR INTEGRATED CIRCUITS
摘要 <p>A novel interconnect layout method and metallization scheme is provided. The process of the present invention provides a multilevel interconnect structure formed solely from patterned metal layers (32, 36) stacked on top of each other. Both interconnect lines which form electrical connections along horizontal paths, as well as contacts which form electrical connections along vertical paths, can be formed using patterned metal interconnects as building-blocks. To form thicker metal layers for the purpose of constructing thick interconnect lines, two or more patterned metal layers may be stacked on each other.</p>
申请公布号 WO1997011488(A1) 申请公布日期 1997.03.27
申请号 US1996013931 申请日期 1996.08.30
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