FABRICATION METHOD OF VERTICAL FIELD EFFECT TRANSISTOR

摘要

A method of fabricating a high-output, vertical field-effect transistor having high switching characteristics, which requires only one step to form an N<+> connection region and an N<-> connection region though two steps are required conventionally. To this end, arsenic is implanted into an N-epitaxial layer by high-energy ion implantation of at least 500 keV. As a result, the vertical impurity distribution through the substrate becomes low (or substantially the same) - high - low (substantially the same) with respecto to the concentration of the N-epitaxial layer.