发明名称 |
An invalidation bus optimisation for multiprocessors using directory-based coherence protocols |
摘要 |
<p>An optimization scheme for a directory-based cache coherence protocol for multistage interconnection network-based multiprocessors improves system performance by reducing network latency. The optimization scheme is scalable, targeting multiprocessor systems having a moderate number of processors. The modification of shared data is the dominant contributor to performance degradation in these systems. The directory-based cache coherence scheme uses an invalidation bus on the processor side of the network. The invalidation bus connects all the private caches in the system and processes the invalidation requests thereby eliminating the need to send invalidations across the network. <IMAGE></p> |
申请公布号 |
EP0764905(A1) |
申请公布日期 |
1997.03.26 |
申请号 |
EP19960306163 |
申请日期 |
1996.08.23 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BAYLOR, SANDRA JOHNSON;HSU, YARSUN |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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