| 摘要 |
Disclosed is an apparatus to monitor performance of a system. The apparatus comprises the first and second input data converter, the first parity/CRC(Cylic Redundancy Check) calculator, a digital data processor, the second parity/CRC calculator, a parity/CRC detector and a comparator. The first and second input data converter convert input data into the data to be processed by the system. The first parity/CRC calculator calculates parity or CRC bit by the data from the second input data converter. The digital data processor processes the data from the first parity/CRC calculator and from the first input data converter. The second parity/CRC calculator calculates parity or CRC bit according to data from the digital data processor. The parity/CRC detector detects the parity or CRC bit from the digital data processor. The comparator campares parity or CRC bit from the parity/CRC detector with that from the second parity/CRC calculator, and generates an error signal. Thereby, the trouble state is perfectly detected according to the duplicating test.
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