摘要 |
<p>An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity (2, 4, 6, 30; 12, 14, 16, 32) with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants (C) in the substrate (38) rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops (CSO) so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads (8, 18, 28, 34) over the transistor array, with a uniform pattern of heavily doped implant taps (ST, DT) from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops. <IMAGE></p> |