发明名称 |
Automatic clock signal phase adjusting circuit utilizing level detector and pattern detector |
摘要 |
An automatic clock signal phase adjusting circuit for use with a digital magnetic recording and reproducing apparatus adopting a partial response class IV coding method. The automatic clock signal phase adjusting circuit comprises: a pattern detection circuit for detecting at least one of patterns "1, 0, -1" and "-1, 0, 1" from a reproduced signal; a level detection circuit for detecting the levels of the reproduced signal in effect when the pattern detection circuit detects 0's; a clock reproduction circuit for reproducing a clock signal from the reproduced signal; and a phase adjustment circuit for adjusting the phase of the clock signal reproduced by the clock reproduction circuit based on the output signal from the level detection circuit.
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申请公布号 |
US5615060(A) |
申请公布日期 |
1997.03.25 |
申请号 |
US19950434064 |
申请日期 |
1995.05.03 |
申请人 |
SONY CORPORATION |
发明人 |
SEKI, TAKAHITO;YOSHIOKA, HARUYUKI |
分类号 |
G11B5/008;G11B5/09;G11B20/10;G11B20/14;H04L7/02;H04L7/04;(IPC1-7):G11B27/36;G11B5/01 |
主分类号 |
G11B5/008 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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