| 摘要 |
A neural processor element for use in a neural network includes a synaptic base weighting circuit which responds to an excitory input in the form of a stream of pulses of a first polarity which represents a sum of synaptic weights and an inhibitory input in the form of a stream of pulses of a second polarity which represents a sum of synaptic weights. The synaptic weight of the neural processor element is generated by summing the excitory and inhibitory pulse streams to produce a signal of varying level magnitude. This signal is subjected to a thresholding function which generates a pulse having a width corresponding to the sum of excitory and inhibitory pulse streams, this pulse width representing the synaptic weight for the neural processor element.
|
