发明名称 |
Latched row decoder for a random access memory |
摘要 |
A latched row decoder for a Random Access Memory (RAM). The Decoder includes a set-reset latch that is set when addressed and remains set until reset by a PRE signal; address select logic; a reset device; and gated word line drives. The latch, when set, enables four word line drivers that are driven individually depending on two row address bits. During test, latched decoders may be selected sequentially and not reset, leaving drivers enabled until a test is complete. Thus some or all word lines may be driven simultaneously during test. A RAM including the latched decoder of the present invention has a normal random access mode and at least 4 test modes. The test modes are: Long tRAS word line disturb mode; toggled word line disturb mode; transfer gate stress mode; and a stress test mode.
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申请公布号 |
US5615164(A) |
申请公布日期 |
1997.03.25 |
申请号 |
US19950477063 |
申请日期 |
1995.06.07 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KIRIHATA, TOSHIAKI;WONG, HING |
分类号 |
G11C11/413;G11C8/10;G11C11/401;G11C11/407;G11C11/408;G11C29/02;G11C29/06;G11C29/12;G11C29/34;G11C29/50;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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