发明名称 Memory reflection system and method for reducing bus utilization and device idle time in the event of faults
摘要 A memory reflection scheme is disclosed including a snarfing agent provided with efficient memory reflection circuitry for snarfing data. The memory reflection circuitry is for snarfing particular data written back from a write back agent to a memory subsystem agent. In response to unsuccessfully snarfing the particular data written back from the write back agent to the memory subsystem agent, the memory reflection circuitry issues a command to read the particular data from the memory subsystem agent. However, the memory reflection circuitry only issues such a command if the write back agent successfully writes back the particular data to the memory subsystem agent.
申请公布号 US5615334(A) 申请公布日期 1997.03.25
申请号 US19940321205 申请日期 1994.10.07
申请人 INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE 发明人 WANG, SHIH-CHIEH;CHANG, WEI-WEN;CHEN, LU-PING
分类号 G06F12/08;(IPC1-7):G06F11/00;G06F12/00 主分类号 G06F12/08
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