发明名称 Self aligned via dual damascene
摘要 An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. In the former, the partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. In the latter, the conductive line openings and vias are filled with the same conductive material.
申请公布号 US5614765(A) 申请公布日期 1997.03.25
申请号 US19950478319 申请日期 1995.06.07
申请人 ADVANCED MICRO DEVICES, INC. 发明人 AVANZINO, STEVEN;GUPTA, SUBHASH;KLEIN, RICH;LUNING, SCOTT D.;LIN, MING-REN
分类号 H01L21/60;H01L21/768;H01L23/522;(IPC1-7):H01L23/48;H01L23/52;H01L29/40 主分类号 H01L21/60
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