| 摘要 |
B-frame processor of a video decoder reduces a memory capacitance for a B-frame processing, performs a video motion compensation of a half-pixel unit in order to a high definition processing in consideration of B-frame, and enhances a coding rate of a video signal. The B-frame processor performs a B-frame processing by using two frame memories and FIFO memory, and performs a B-frame processing by using B-frame image by using two frame memories without using the FIFO memory, reduces a memory capacitance and a production cost, a simplifies a circuit, thereby enhancing a HDTV quality. The B-frame processor includes: first and second read address generator(6,7) for generating a read address of frame memories(12,13); a first write address generator(8) for generating a write address of frame memories(12,13); first and second multiplexers(9,10) for selectively outputting the read or write address; first and second frame memories(12,13) in which a motion compensation of a pixel unit is achieved; a bidirectional latch(14) for storing/outputting a frame image of the frame memories(12,13); an averaging part(21) for averaging about the output signal of the bidirectional latch(14); a delay regulation and selector(22) for selectively outputting a compensated signal from the frame memory(12), a compensated signal from the frame memory(13), an average siganl from the averaging part(21); an adder(23) for adding the IDCT output signal to an output signal of the delay regulation and selector(22); third and fourth frame memories(24,25) for storing an output video signal from the delay regulation and selector(22); a delay regulator(26) for regulating a delat time of the output video signal from the frame memories(24,25); a slice buffer(27); a second write address generator(30); and a sixth multiplexer(32). |
