MEMORY CONTROLLER WITH LOW SKEW CONTROL SIGNAL

摘要

An apparatus and a method are provided for delaying or skewing (70) a control signal provided to an electronic device such as a memory device (40) with an alignment delay, such that the overall delay associated with the alignment delay and the propagation delay associated with outputting (75) the control signal (70) to the electronic device substantially equals one or more integral cycles of a clock signal. As a result, the control signal (70) received at the electronic device (40) is substantially aligned with the clock signal. This results in synchronizing or realigning the asynchronously generated control signal back into a synchronous environment. The apparatus and method have unique applicability when used in memory controllers (60) and the like for handling memory accesses with one or more memory devices, in particular with memory devices having enhanced memory transfer modes or higher transfer speeds.