| 摘要 |
An SRAM array configuration includes even bitline pairs which each laterally interchange at a crossover placed at the 1/2 point along the length of the bitline pairs, and which SRAM array includes odd bitline pairs which each laterally interchange at each of two associated crossovers at the 1/4 and 3/4 points along the length of the bitline pairs. Consequently, signals or noise resident on neighboring bitline pairs or other neighboring conductive structure couple a common-mode voltage onto a given bitline pair through lateral parasitic capacitance to the neighboring conductive structure. Such a common-mode noise signal does not affect the differential signal on the given bitline pair. This interlace configuration is useful for one or more pairs of differential signal lines, whether used within an SRAM array or for global interconnect between circuit blocks. |
