Method of manufacturing first and second memory cell arrays with a capacitor and a nonvolatile memory cell

摘要

A DRAM includes a main section including a DRAM memory cell array including a plurality of DRAM cells arranged in an array, a spare section including a Spare DRAM memory cell array including a plurality of DRAM memory cells arranged in an array, an address decoder for specifying addresses respectively of the DRAM memory cell array and the spare DRAM memory cell array, and a defective bit replacement control circuit which is connected to the address decoder and which includes a plurality of electrically rewritable nonvolatile memory cells.