| 摘要 |
A counter circuit provides select signals SEL0-SEL3 of a cycle 4Tc sequentially attaining a high level for every +E,fra 1/4+EE cycle Tc. A 4-input selector circuit receives data signals I0-I3 of a cycle 4Tc to sequentially output the same for every +E,fra 1/4+EE period of Tc in response to a high level of select signals SEL0-SEL3. A flipflop circuit fetches and outputs an output of the selector circuit in synchronization with a clock signal C0. The number of hardware components is reduced in comparison with the conventional case where a select signal generation circuit generates only one select signal SEL, and where a plurality of flipflop circuits and 2-input selector circuits carry out a select and shifting operation of parallel data signals I0-I3.
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