发明名称 DATA MEMORY
摘要 <p>PROBLEM TO BE SOLVED: To shorten the execution time of a CPU by providing a pulse generating circuit generating a data write signal and a counter setting memory addresses and obviating labor and time of data reading and writing and of address setting by the CPU. SOLUTION: A data conversion circuit 1 outputs data obtained by converting a waveform signal and contact point signal 101 to data busses 102. The data are written in a memory 3' by the write signal 104' from a pulse generating circuit 4 and simultaneously a counter 5 counts the write signal 104' to update the address on an address busses 103'. When a CPU 2' performs a data reading operation, the data are read from the memory 3' into the CPU 2' by a read signal 105' and, at the same time, the counter 5 counts the read signal 105' to update the address on the address busses 103'. Thus, the load of the CPU 2' is reduced and the execution time of the CPU 2' is shortened.</p>
申请公布号 JPH0973771(A) 申请公布日期 1997.03.18
申请号 JP19950255541 申请日期 1995.09.07
申请人 TOYO ELECTRIC MFG CO LTD 发明人 NONOMURA YOSHIO
分类号 G11C7/00;(IPC1-7):G11C7/00 主分类号 G11C7/00
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