发明名称 DECODER AND MPEG VIDEO DECODER
摘要 <p>PROBLEM TO BE SOLVED: To realize an MPEG video decoder simple in configuration and capable of avoiding overflow of a bit buffer without degrading picture quality at the time of a high speed reproduction. SOLUTION: A picture skip circuit 6 is connected to the side of a node 6a at the time of a normal reproduction and transfers each picture read from a bit buffer 2 as is to a decode core circuit 4. In the picture skip circuit 6, the connection to the side of each node 6a and 6b is switched in accordance with the controls of a picture header detection circuit 3 and a decision circuit 5, each picture read from the bit buffer 2 is thinned by a picture unit and the picture is transferred to the decode core circuit 4. Namely, when the picture skip circuit 6 is connected to the side of the node 6b, the picture read from the bit buffer 2 is skipped without being transferred to the decode core circuit 4.</p>
申请公布号 JPH0974557(A) 申请公布日期 1997.03.18
申请号 JP19950271377 申请日期 1995.10.19
申请人 SANYO ELECTRIC CO LTD 发明人 OKADA SHIGEYUKI;KAWAHARA KEITA
分类号 H04N5/92;G06T9/00;G11B20/10;H03M7/30;H04N19/00;H04N19/132;H04N19/134;H04N19/172;H04N19/186;H04N19/196;H04N19/423;H04N19/44;H04N19/50;H04N19/85;(IPC1-7):H04N7/24;H04N7/32 主分类号 H04N5/92
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