| 摘要 |
An apparatus for testing and connecting integrated circuit chips to external packaging and circuitry. A plurality of electrically conductive leads are formed on an electrically insulative substrate by tape automated bonding methods. The leads extend from peripherally disposed test terminals to centrally disposed interconnect pads and are aligned therebetween with bond pads that are disposed near a perimeter of a face of a chip. The leads are connected to the bond pads and are encapsulated with a cement, and the substrate is adhered to the chip face. Electronic characteristics of the chip are tested by channeling electrical signals via the test terminals. The leads are then severed closely peripheral to the bond pads, disconnecting the test terminals from the chip. The chips that pass the testing are connected via the interconnect pads, which may be arranged in a pad grid array, to matching terminals in a package. After severing, an electrically insulative resist may be deposited on the leads but not on the interconnect pads, and electrically conductive bumps deposited on the interconnect pads for connection with the package terminals.
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