发明名称
摘要 A flipflop has master and slave interconnected through a buffer. The master has its inverters located outside the signal path from input to output, as the buffer provides the driving capability required for both IDDQ-testing and operational use. This configuration enables IDDQ-testing without further circuitry added to the flipflop and reduces propagation delay in the signal path.
申请公布号 JPH09502808(A) 申请公布日期 1997.03.18
申请号 JP19960503764 申请日期 1995.06.29
申请人 发明人
分类号 G01R31/317;G01R31/28;G01R31/30;G01R31/3185;G06F11/267;H03K3/037 主分类号 G01R31/317
代理机构 代理人
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