| 摘要 |
The circuit has each calibration loop formed with a common delay time counter (82), OR gate (75) and buffer (76), delay elements (78,55), gate circuits (52,56) and coaxial cables (40,45). A pulse from the clock generator (90) circulates in a feedback loop in accordance with a delay for each test channel. The delay time is adjusted to be equal to a basic delay or a delay in another loop. Each loop has an output connection to an associated signal path, and the delays in all loops are brought to a constant value.
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