Dual-mode automatic test equipment especially for integrated circuits

摘要

The equipment prepares a sequence of events in accordance with the selected mode. It includes first and second start memories (ESSM01,ESSM23) of equal size, sequence memories (ESS01,ESS23) also of equal size and logic reacting to the operational mode signal (AM). The logic comprises selectors (340,354,356) and a gate (355) which in the normal mode apply a single address from the start memories to both sequence memories. In the accelerated mode the memories are coupled differently so that each start memory supplies a different address to the corresponding sequence memory.