OUTPUT BUFFER INCORPORATING SHARED INTERMEDIATE NODES

摘要

An output buffer is disclosed for an integrated circuit having a varying number of simultaneously switching outputs. As fewer outputs on the integrated circuit are simultaneously switching, the ouput conductance of certain logic gates within each of the output buffers on the integrated circuit is increased by sharing intermediate nodes (PUCOM, PDCOM) between each of the output buffers. Consequently, the speed of the output buffer increases as fewer of the outputs simultaneously switch and internally generated noiseis small. Conversely, as additional outputs simultaneously switch, the output conductance of certain logic gates within the output buffer is decreased, resulting in reduced speed of the output buffers and a corresponding reduction in internally generated noise.