Fuzzy logic controller with a high processing speed

摘要

The invention relates to a fuzzy logic controller which consists of a fuzzification circuit (FUZ), a rule decoder (RDEC), a rule evaluating circuit (RA), an inference circuit (INF), a defuzzification circuit (DFUZ) and a sequence controller (CTRL), in which arrangement numbers (NA) for linguistic values of the output variables, together with selection signals (SM) for determining the input variables affected by the respective rule can be formed in the rule decoder and can be supplied, in addition to the values (ME) of the match functions for linguistic values of the input variables, to the rule evaluating circuit where a weighting signal (G) can be generated for each linguistic value of the output variables. The advantages which can be achieved by means of the invention lie especially in the high processing speed, in the small chip area required, in the variable rule format and in the possibility of selecting different operating modes in the rule evaluation circuit, in the inference circuit and in the defuzzification circuit.