| 摘要 |
An ECC decoder detects a no error, a correctable error or an uncorrectable error state and reports to art upper controller after user data is read. A state indicative of the completion of the correction, an erroneous correction, or an abnormal operation is detected and logged for every process of a subblock unit in the ECC decoder, thereby enabling such a state to be referred from the upper controller. An error detection code is provided after the user data to detect a non-detection or an erroneous correction of errors when errors exceed the correcting ability of the ECC decoder. Further, a circuit to obtain values gamma n0 to gamma nn to decide solutions beta k of simultaneous equations of (n) unknowns by the ECC decoder is formed by sequentially coupling from an arithmetic operating circuit of one unknown to an arithmetic operating circuit of (n) unknowns. An error location arithmetic operating circuit for each of a fixed and a variable length subblock is provided for the ECC decoder. The variable length subblock presumes the start location of the fixed length subblock and executes a dummy search of the arithmetic operating circuit and switches to an ordinary error search at the start location of the variable subblock. When a header and counting section at the record head is discriminated, the delay time is switched to the short delay time according to the block length, thereby preventing a large delay corresponding to the fixed length subblock of the record.
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